AMD Strix & Strix Halo APU Official Docs Allegedly Leak: Up To 16 Zen 5 Cores, 40 RDNA 3+ iGPU, 60 AI TOPs, LPDDR5x-8000, 32 MB MALL

25.04.2024 - 11:37 / wccftech.com / Hassan Mujtaba

An alleged "official" AMD document with information regarding AMD's Zen 5-powered Strix & Strix Halo APU has leaked out, spilling the beans on the full platform details for the red team's next-gen mobility lineup.

AMD Strix & Strix Halo APUs To Mark A Major Update For The Ryzen Mobility Lineup: Featuring Zen 5 CPU, RDNA 3+ iGPU & XDNA 2 AI NPU Cores

The leak comes from HKEPC who managed to spot the official AMD documents posted over at X by a user known as Izzukias. The original post has been removed but the tech outlet managed to get a good grasp of things and even shared the specs page for the Strix & Strix Halo lineup which will be featuring the next-gen Zen 5 CPU, RDNA 3+ iGPU and XDNA 2 NPU cores. Let's start off with the full details.

Related Story AMD Strix Point “Zen 5” APU Tested Again, 12-Core & 2.3 GHz ES Ryzen Chip Now Ahead of Fastest Phoenix & Hawk Point APUs

AMD Strix (1) APU Specifications & Platform Details

First up, we have the AMD Strix (Strix Point 1) family which will be using the standard monolithic APU design. These chips will be fabricated on the TSMC 4nm process node and will come in SKUs with up to 12 cores and 24 threads. We have seen several engineering samples leak out so far.

As for the cache, the APUs will adopt 12 MB of L2 cache (1 MB per core) and 24 MB of L3 cache which will be partitioned into 8 MB for Zen 5C and 16 MB for Zen 5 cores. The chips will also feature 32 KB of L1 Instruction cache and increase 48 KB of L1 Data cache (32 KB on Zen 4). The APUs will offer 16 PCie Gen 4 lanes.

For memory support, the Ryzen Strix APUs will feature support of up to LPDDR5-7500 & DDR5-5600 memory which is the standard affair for most mainstream laptops. The next-gen Ryzen AI-engine is going to offer up to 50 TOPS (XDNA 2). AMD internally seems to refer to this as AIE2+ or AI Engine 2 Plus.

On the iGPU side, we will see a total of 8 RDNA 3+ WGPs or 16 compute units. We have so far seen this chip clock up to 2.6 GHz in early samples so the final silicon can end up around 3 GHz+. These APUs were once supposedly going to feature 16 MB of MALL cache. All of the AMD Strix Point 1 APUs will be designed around the FP8 socket. It is reported that the Strix APU family will feature TDPs between 45-65W which can be configured down to 28W.

AMD Ryzen 9050 Strix Mono Expected Features:

• Zen 5 (4nm) Monolithic Design
• Up To 12 Cores In Hybrid Config (Zen 5 + Zen 5C)
• 24 MB L3 cache / 12 MB L2 Cache
• 16 RDNA 3+ Compute Units
• LPDDR5-7500/DDR5-5600 support
• XDNA 2 Engine Integrated
• Up To 50 AI TOPS
• 16 PCIe Gen4 Lanes
• 2H 2024 Launch (Expected)
• FP8 Platform (28W-65W)

AMD Strix Halo APU Specifications & Platform Details

The AMD Strix Halo APUs will be the chiplet offerings, utilizing up to 3 dies, 2 CCDs